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https://en.wikipedia.org/wiki/RISC-V
國科大本科生9個月設計出處理器晶元 可運行Linux系統
2020年07月25日 16:08 新京報網
原標題:“一生一芯” 國科大本科生帶著自己設計的晶元畢業
新京報訊(記者 樊朔)7月25日,中國科學院大學公布了該校首期“一生一芯”計劃成果。該成果在國內首次以流片為目標,由五位2016級本科生主導完成了一款64位RISC-V處理器SoC晶元的設計並實現了流片。晶元可以成功運行Linux操作系統以及學生自己編寫的國科大教學操作系統UCAS-Core。
經過9個月的努力,國科大2016級計算機學院本科生金越、王華強、王凱帆、張林雋和張紫飛帶著自己設計的晶元畢業。 圖源:中國科學院大學
據了解,國科大於2019年8月啟動了“一生一芯”計劃,目標是通過讓本科生設計處理器晶元並完成流片,培養具有紮實理論與實踐經驗的處理器晶元設計人才。國科大計算機科學與技術學院院長、中國科學院計算技術研究所所長孫凝暉院士宣布,經過9個月的努力,由國科大2016級計算機學院本科生金越、王華強、王凱帆、張林雋和張紫飛參與的首期“一生一芯”計劃取得圓滿成功,五位本科生實現帶著自己設計的處理器晶元畢業這一目標。
“一生一芯”計劃負責人、國科大計算機學院教授、中科院計算所先進計算機系統研究中心主任包雲崗介紹,學生們將這款處理器晶元命名為“果殼(NutShell)”,與“國科”發音相同,希望通過自己設計的處理器晶元來寄託對國科大深厚的情感。包雲崗向媒體透露,RISC-V全球論壇剛剛接收了“果殼”團隊的投稿,王華強同學將代表團隊於9月3日向全球業界介紹“果殼”的設計。“這是‘果殼’首次在國際舞台上亮相。RISC-V全球論壇的報告均來自世界各地的業界資深專家,包括圖靈獎得主David Patterson教授。”
孫凝暉表示,處理器晶元被公認為晶元產業皇冠上的明珠,設計複雜度高、難度大。我國處理器晶元設計人才嚴重緊缺,如何加快此類人才的培養規模與培養速度,是我國迫在眉睫的難題。針對處理器設計人才危機, “一生一芯”計劃的願景目標是在國科大實踐經驗的基礎上向全國輻射,幫助更多高校形成從處理器晶元設計到流片並運行操作系統的實踐課程,提高我國處理器晶元設計人才培養規模,縮短人才從培養階段到投入科研與產業一線的周期,力爭實現3年後在全國每年能培養500名學生,5年後實現每年培養1000名學生,10年達到每年培養1萬名學生。
新京報記者 樊朔 校對 劉軍
開源架構的實現 Implementations
The RISC-V organization maintains a list of RISC-V CPU and SoC implementations.[45]
已有 Existing
Existing commercial implementations include:
- Alibaba Group, in July 2019 announced the 2.5 GHz 16-core 64-bit (RV64GCV) XuanTie 910 out-of-order processor, the fastest RISC-V processor to date[46]
- Andes Technology Corporation, a founding member of RISC-V International[47] which joined the consortium in 2016, released its first two RISC-V cores in 2017. The cores, the N25 and NX25, come with a complete design ecosystems and a number of RISC-V partners. Andes is actively driving the development of RISC-V ecosystem and expects to release several new RISC-V products in 2018.
- CloudBEAR is a processor IP company that develops its own RISC-V cores for a range of applications.[48]
- Codasip and UltraSoC have developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip's RISC-V cores and other IP with UltraSoC's debug, optimization and analytics.[49]
- Cortus, a founding platinum member of the RISC-V foundation, has a number of RISC-V implementations and a complete IDE/toolchain/debug eco-system which it offers for free as part of its SoC design business.
- GigaDevice has a series of MCUs based on RISC-V (RV32IMAC, GD32V series),[50] with one of them used on the Longan Nano board produced by a Chinese electronic company Sipeed.[51]
- GreenWaves Technologies announced the availability of GAP8, a 32-bit 1 controller plus 8 compute cores, 32-bit SoC (RV32IMC) and developer board in February 2018. Their GAPuino GAP8 development board started shipping in May 2018.[52][53][54]
- IAR Systems released the first version of IAR Embedded Workbench for RISC-V, which supports RV32 32-bit RISC-V cores and extensions in the first version. Future releases will include 64-bit support and support for the smaller RV32E base instruction set, as well as functional safety certification and security solutions.
- Instant SoC RISC-V cores from FPGA Cores. System On Chip, including RISC-V cores, defined by C++.
- SEGGER added support for RISC-V cores to their debug probe J-Link,[55] their integrated development environment Embedded Studio,[56] and their RTOS embOS and embedded software.[57]
- SiFive, a company established specifically for developing RISC-V hardware, has processor models released in 2017.[58][59] These include a quad-core, 64-bit (RV64GC) system on a chip (SoC) capable of running general-purpose operating systems such as Linux.[60]
- Syntacore,[61] a founding member of RISC-V International and one of the first commercial RISC-V IP vendors, develops and licenses family of RISC-V IP since 2015. As of 2018, product line includes eight 32- and 64-bit cores, including open-source SCR1 MCU core (RV32I/E[MC]).[62] First commercial SoCs, based on the Syntacore IP were demonstrated in 2016.[63]
- UltraSOC proposed a standard trace system and donated an implementation.
- Western Digital, in December 2018 announced an RV32IMC core called SweRV. The SweRV features an in-order 2-way superscalar and nine-stage pipeline design. WD plans to use SweRV based processors in their flash controllers and SSDs, and released it as open-source to third parties in January 2019.[64][65][66]
- Espressif[67] added a RISC-V ULP coprocessor to their ESP32-S2 microcontroller.[68]
在研 In development
- ASTC developed a RISC-V CPU for embedded ICs.[69]
- Centre for Development of Advanced Computing, India (C-DAC) is developing a 64-bit out-of-order quad-core RISC-V processor.[70]
- Cobham Gaisler NOEL-V 64-bit. [71]
- Computer Laboratory, University of Cambridge, in collaboration with the FreeBSD Project, has ported that operating system to 64-bit RISC-V to use as a hardware-software research platform.[72]
- Esperanto Technologies announced that they are developing three RISC-V based processors: the ET-Maxion high-performance core, ET-Minion energy-efficient core, and ET-Graphics graphics processor.[73]
- ETH Zurich and the University of Bologna have cooperatively developed the open-source RISC-V PULPino processor[74] as part of the Parallel Ultra-Low Power (PULP) project for energy-efficient IoT computing.[75]
- European Processor Initiative (EPI), RISC-V Accelerator Stream.[76][77]
- Indian Institute of Technology Madras is developing six RISC-V open-source CPU designs for six distinct uses, from a small 32-bit CPU for the Internet of Things (IoT) to large, 64-bit CPUs designed for warehouse-scale computers such as server farms based on RapidIO and Hybrid Memory Cube technologies.[12][78]
- lowRISC is a non profit project to implement a fully open-source hardware system on a chip (SoC) based on the 64-bit RISC-V ISA.[79]
- Nvidia plans to use RISC-V to replace their Falcon processor on their GeForce graphics cards.[80]
- SiFive announced their first RISC-V out-of-order high performance CPU core, the U8 Series Processor IP.[81]
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