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国科大本科生9个月设计出处理器芯片 可运行Linux系统


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开源指令集 。

有多家硬件商出品。

https://en.wikipedia.org/wiki/RISC-V

 


国科大本科生9个月设计出处理器芯片 可运行Linux系统

2020年07月25日 16:08 新京报网

  原标题:“一生一芯” 国科大本科生带着自己设计的芯片毕业

  新京报讯(记者 樊朔)7月25日,中国科学院大学公布了该校首期“一生一芯”计划成果。该成果在国内首次以流片为目标,由五位2016级本科生主导完成了一款64位RISC-V处理器SoC芯片的设计并实现了流片。芯片可以成功运行Linux操作系统以及学生自己编写的国科大教学操作系统UCAS-Core。

  经过9个月的努力,国科大2016级计算机学院本科生金越、王华强、王凯帆、张林隽和张紫飞带着自己设计的芯片毕业。 图源:中国科学院大学

  据了解,国科大于2019年8月启动了“一生一芯”计划,目标是通过让本科生设计处理器芯片并完成流片,培养具有扎实理论与实践经验的处理器芯片设计人才。国科大计算机科学与技术学院院长、中国科学院计算技术研究所所长孙凝晖院士宣布,经过9个月的努力,由国科大2016级计算机学院本科生金越、王华强、王凯帆、张林隽和张紫飞参与的首期“一生一芯”计划取得圆满成功,五位本科生实现带着自己设计的处理器芯片毕业这一目标。

  “一生一芯”计划负责人、国科大计算机学院教授、中科院计算所先进计算机系统研究中心主任包云岗介绍,学生们将这款处理器芯片命名为“果壳(NutShell)”,与“国科”发音相同,希望通过自己设计的处理器芯片来寄托对国科大深厚的情感。包云岗向媒体透露,RISC-V全球论坛刚刚接收了“果壳”团队的投稿,王华强同学将代表团队于9月3日向全球业界介绍“果壳”的设计。“这是‘果壳’首次在国际舞台上亮相。RISC-V全球论坛的报告均来自世界各地的业界资深专家,包括图灵奖得主David Patterson教授。”

  孙凝晖表示,处理器芯片被公认为芯片产业皇冠上的明珠,设计复杂度高、难度大。我国处理器芯片设计人才严重紧缺,如何加快此类人才的培养规模与培养速度,是我国迫在眉睫的难题。针对处理器设计人才危机, “一生一芯”计划的愿景目标是在国科大实践经验的基础上向全国辐射,帮助更多高校形成从处理器芯片设计到流片并运行操作系统的实践课程,提高我国处理器芯片设计人才培养规模,缩短人才从培养阶段到投入科研与产业一线的周期,力争实现3年后在全国每年能培养500名学生,5年后实现每年培养1000名学生,10年达到每年培养1万名学生。

  新京报记者 樊朔 校对 刘军


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开源架构的实现 Implementations

The RISC-V organization maintains a list of RISC-V CPU and SoC implementations.[45]

已有 Existing

Existing commercial implementations include:

  • Alibaba Group, in July 2019 announced the 2.5 GHz 16-core 64-bit (RV64GCV) XuanTie 910 out-of-order processor, the fastest RISC-V processor to date[46]
  • Andes Technology Corporation, a founding member of RISC-V International[47] which joined the consortium in 2016, released its first two RISC-V cores in 2017. The cores, the N25 and NX25, come with a complete design ecosystems and a number of RISC-V partners. Andes is actively driving the development of RISC-V ecosystem and expects to release several new RISC-V products in 2018.
  • CloudBEAR is a processor IP company that develops its own RISC-V cores for a range of applications.[48]
  • Codasip and UltraSoC have developed fully supported intellectual property for RISC-V embedded SOCs that combine Codasip's RISC-V cores and other IP with UltraSoC's debug, optimization and analytics.[49]
  • Cortus, a founding platinum member of the RISC-V foundation, has a number of RISC-V implementations and a complete IDE/toolchain/debug eco-system which it offers for free as part of its SoC design business.
  • GigaDevice has a series of MCUs based on RISC-V (RV32IMAC, GD32V series),[50] with one of them used on the Longan Nano board produced by a Chinese electronic company Sipeed.[51]
  • GreenWaves Technologies announced the availability of GAP8, a 32-bit 1 controller plus 8 compute cores, 32-bit SoC (RV32IMC) and developer board in February 2018. Their GAPuino GAP8 development board started shipping in May 2018.[52][53][54]
  • IAR Systems released the first version of IAR Embedded Workbench for RISC-V, which supports RV32 32-bit RISC-V cores and extensions in the first version. Future releases will include 64-bit support and support for the smaller RV32E base instruction set, as well as functional safety certification and security solutions.
  • Instant SoC RISC-V cores from FPGA Cores. System On Chip, including RISC-V cores, defined by C++.
  • SEGGER added support for RISC-V cores to their debug probe J-Link,[55] their integrated development environment Embedded Studio,[56] and their RTOS embOS and embedded software.[57]
  • SiFive, a company established specifically for developing RISC-V hardware, has processor models released in 2017.[58][59] These include a quad-core, 64-bit (RV64GC) system on a chip (SoC) capable of running general-purpose operating systems such as Linux.[60]
  • Syntacore,[61] a founding member of RISC-V International and one of the first commercial RISC-V IP vendors, develops and licenses family of RISC-V IP since 2015. As of 2018, product line includes eight 32- and 64-bit cores, including open-source SCR1 MCU core (RV32I/E[MC]).[62] First commercial SoCs, based on the Syntacore IP were demonstrated in 2016.[63]
  • UltraSOC proposed a standard trace system and donated an implementation.
  • Western Digital, in December 2018 announced an RV32IMC core called SweRV. The SweRV features an in-order 2-way superscalar and nine-stage pipeline design. WD plans to use SweRV based processors in their flash controllers and SSDs, and released it as open-source to third parties in January 2019.[64][65][66]
  • Espressif[67] added a RISC-V ULP coprocessor to their ESP32-S2 microcontroller.[68]

在研 In development


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